Computer Organization and Architecture
24CSP305 · S3 · 4 credits
Official KTU 2024 syllabus subject — study with practice, PYQs and AI tools.
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Why:Applied concepts
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Module 01Instruction Set Architecture (7 hours)expand
Review of number representation and operations. Basic operational concepts. Instruction Set Architecture - CPU registers, Memory location and addresses, Instruction sequencing, Instruction format and encoding, addressing modes.
Module 02The Processor (11 hours)expand
Reduced Instruction Set Computer (RISC) vs Complex Instruction Set Computer (CISC), RISC-V instructions overview. CPU Performance - Amdahl’s law, Building a data path and control, Single cycle processor, Multi-cycle processor, An Overview of Pipelining - Instruction pipelining, Notion of ILP, Data and control hazards and their mitigations.
Module 03Introduction to Memory Hierarchy (6 hours)expand
Memory Technologies- SRAM/DRAM/Flash. Memory Hierarchy, Locality of reference, The Basics of Caches – handling misses and writes. Trade-offs related to block size, associativity, and cache size.
Module 04Memory Level Optimization (7 hours)expand
Measuring and improving cache performance - Average memory access time, Basic optimizations - Reducing Cache Misses, Reducing miss penalty, Software optimization. Cache replacement policies (LRU). Introduction to multicore systems and cache coherence
Module 05Storage and I/O (5 hours)expand
Introduction to magnetic disks (notion of tracks, sectors). Accessing I/O devices, Interrupts, I/O mapped I/O, Memory mapped I/O. I/O data transfer techniques - programmed I/O, Interrupt-driven I/O, and DMA.
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