Digital Electronics and Logic Design
24ERJ303 · S3 · 5 credits
5 modules · Practice & PYQs ready
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Why:2 high-weightage exam questions · Formula-heavy module · Many definitions to memorize · Has worked numerical examples
Why:2 high-weightage exam questions · Formula-heavy module · Many definitions to memorize · Has worked numerical examples · Foundation module
Why:3 high-weightage exam questions · Many definitions to memorize
Why:2 high-weightage exam questions · Formula-heavy module · Many definitions to memorize · Has worked numerical examples
Why:2 high-weightage exam questions · Formula-heavy module · Many definitions to memorize
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M1Number Systems and Logic Gate Fundamentals
Convert a given number between binary, octal, decimal and hexadecimal.
Represent a given decimal number in sign-magnitude, 1's complement and 2's complement form, and perform addition/subtraction using 2's complement.
Encode a given decimal number in BCD, Excess-3, and Gray code.
Explain the working of a parity bit for error detection with an example.
Differentiate TTL and CMOS logic families.
Differentiate fixed-point and floating-point number representation.
M2Boolean Algebra and Combinational Circuit Design
Simplify a given 4-variable Boolean expression using a K-map (with or without don't-care terms), and draw the resulting logic circuit.
Design and draw a full adder / full subtractor circuit, deriving its truth table and Boolean expressions.
Design a 4-bit parallel binary adder/subtractor and explain the ripple-carry delay problem.
Explain how a carry look-ahead adder eliminates ripple-carry delay.
Convert a given Boolean expression between SOP and POS form.
M3Digital Logic Components and Verilog Programming
Write Verilog code (gate-level, dataflow, or behavioral) for a given combinational circuit (half/full adder, mux, demux, decoder, encoder).
Differentiate multiplexer, demultiplexer, encoder, and decoder, with their input/output sizing relationships.
Design a BCD-to-seven-segment decoder and explain its working.
Explain the block-level architecture of an ALU.
Write a Verilog testbench for a given basic gate or combinational module.
M4Flip-Flops, Registers, and Counters: Sequential Logic Design
Convert one flip-flop type into another (e.g. design a JK flip-flop using a D flip-flop) using an excitation table and K-map.
Design a synchronous Mod-N counter (state table → excitation table → K-map → logic circuit).
Design and explain a ripple (asynchronous) counter, identifying its propagation delay limitation.
Explain the working of a ring counter and a Johnson counter, including their state counts.
Differentiate the four shift register configurations (SISO, SIPO, PISO, PIPO).
Explain the race-around condition in a JK flip-flop and how a master-slave configuration solves it.
M5State Machines, D/A and A/D Converters, Programmable Logic Devices
Differentiate Moore and Mealy machines, and draw the state diagram for a given sequence detector.
Explain the R-2R ladder DAC and why it's preferred over the weighted-resistor DAC.
Differentiate flash ADC and successive approximation ADC in terms of speed and hardware complexity.
Differentiate PAL, PLA, and FPGA.
Implement a given Boolean function using a PAL or PLA.
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What this module covers
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